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Signal Interface
The pinout of the Fast 100 Mbps Ethernet PICtail Plus depends upon the jumper settings
and which physical connector is used.
PICtail Daughter Board Dual Row Right Angle Header (J3, J4, J5)
The J3 and J4 headers are designed to provide an SPI interface to the PIC18 Explorer and
PICDEM.net 2 Development Boards. The J5 connector is not used; holes for J5 are present
only to aid physical alignment. The PICtail Daughter Board is not wired to permit the
ENC624J600 to interface to the PIC18 Explorer or PICDEM.net 2 using any Parallel modes.
When using the PICtail Daughter Board header, the pinout is as shown in the following table:
Pinout for the PICtail? Daughter Board Header
Signal Name on Board
J3
Pin
—
—
5
J4
Pin
4
5
—
PICtail?
Daughter
Board
5VEXT
GND
OSC1_PIC
PIC18
Explorer
+5V
GND
OSC1
PICDEM.net? 2
—
—
—
Function
5V Power
Ground Reference
CLKOUT to PIC ? MCU (optional) (1)
8
10
12
17
19
21
23
—
—
—
—
—
—
—
SI/RD/RW
SO_VPIC
SCK/AL
SHDN
MDIX
CS/CS
INT_VPIC
RC5/SDO1
RC4/SDI1
RC3/SCK1
RB5
RB4
RB3
RB2/INT2
SPI Data from PIC MCU
SPI Data to PIC MCU
SPI Clock from PIC MCU
Shutdown from PIC MCU
Ethernet Crossover from PIC MCU
SPI Chip Select from PIC MCU
Interrupt to PIC MCU
26
28
—
—
VPIC
GND
V_VAR
GND
+5V
5V Power
Ground Reference
Note 1:
To enable CLKOUT, JP3 must be shorted.
If using the PIC18 Explorer with a PIM installed, be sure to check the PIM schematics for
any renamed or remapped pins.
PICtail Plus (SPI, J2)
The J2 board edge contacts are designed to provide an SPI interface to the Explorer 16 and
PIC32 I/O Expansion Boards. The J2 board edge is keyed such that there are only three
possible ways to insert it into the Explorer 16 and PIC32 I/O expansion slot:
1. Pin 1 on J2 aligns with Pin 1 on host motherboard – use SPI1 pinout.
2. Pin 1 on J2 aligns with Pin 33 on host motherboard – use SPI2 pinout.
3. Pin 1 on J2 aligns with Pin 94 on host motherboard – illegal, do not connect.
4
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